Synchronising Serial Data Signals

ABSTRACT

A method and apparatus for synchronising a serial data signal to a reference clock signal, the data signal comprising frames of equal length each comprising a known frame alignment word (FAW) and a payload, the frame alignment word being in a consistent position within each frame, the method comprising: storing the signal in a FIFO wander buffer as it is received in order to compensate for any wander that may occur; outputting the data signal stored in the FIFO wander buffer synchronised to the reference clock signal; searching for at least a portion of the frame alignment word in the data signal as it is received; and when it is determined that the frame alignment word has been found, realigning the data signal within the wander buffer The step of realigning the data may comprise replacing at least a portion of the data signal in the wander buffer with a locally-held copy of at least a portion of the frame alignment word. The method may be used in any synchronous serial data stream, such as SDH or SONET.

FIELD OF THE INVENTION

The present invention relates to a method and circuit for synchronisinga serial data signal to a reference clock signal, and especially but notexclusively to their application to SDH/SONET data streams.

BACKGROUND OF THE INVENTION

To achieve the data densities required in modern telecommunicationsequipment, internal data interfaces are now very high speed differentialserial data with implicit clock and frame alignment. One approachrequires that all data signals are synchronous to a system referenceclock and frame signal that is distributed to all cards within a pieceof equipment separately. Each receiving element requires a Clock DataRecoverer (CDR) which uses the edges in the incoming data to recover anindependent receive clock, using the local system clock as a guide. Therecovered clock and data are de-serialised and the content can then bealigned to the system frame.

Not all systems, or indeed all technologies (ASIC/FPGA, for example)provide a CDR function. For cost reasons, some systems or technologiesonly offer a “dynamic phase aligner” (DPA) in place of the CDR. The DPAdoes not supply the recovered clock signal, but adapts the incoming datato the system clock using a FIFO (first in, first out) memory. Thus,DPAs are only able to cope with a certain amount of “wander”, where thebit transitions in the incoming signal are not correctly aligned withthe system clock; this can be due to the inherent delays in transmissionover a line, the delays through input or output buffers, noise, etc.These delays are temperature and supply dependent, so will vary overtime.

The DPA provides a “wander buffer” using the area of FIFO memory inwhich it stores data before it is aligned with the system clock; inSDH/SONET systems it is common to have wander buffer capable of holdingsufficient data to cope with a wander in either the fast or slowdirections of 20 ns. However, given the cost implications of providingsufficient memory to do so, some manufacturers are only providing 2.5 nsof wander buffer in order to reduce costs.

A problem with this is that wander is cumulative; from a given devicebeing brought into service it is generally only possible to track themaximum amount of wander so, if wander accrues in a single directionover a period of time, the wander buffer may fill and so data be lost.Generally, the only way to empty the wander buffer is to reset theequipment in question.

SUMMARY OF THE INVENTION

According to a first aspect of the present invention there is provided amethod of synchronising a serial data signal to a reference clocksignal, the data signal comprising frames of equal length eachcomprising a known frame alignment word (FAW) and a payload, the framealignment word being in a consistent position within each frame, themethod comprising:

-   -   storing the signal in a FIFO wander buffer as it is received in        order to compensate for any wander that may occur;    -   outputting the data signal stored in the FIFO wander buffer        synchronised to the reference clock signal;    -   searching for at least a portion of the frame alignment word in        the data signal as it is received; and    -   when it is determined that the frame alignment word has been        found, realigning the data signal within the wander buffer.

Accordingly, this method takes account of the fact that the framealignment is inherently found in the same position within each frame andso the wander buffer can be “reset” when it is found. This prevents databuilding up within the FIFO wander buffer and hence reduces thelikelihood of an overflow occurring; wander need not be allowed to buildup frame after frame. Only as much wander need be tracked as may occuras often as the method is repeated, which is typically every frame.Furthermore, no separate clock recovery device is required, therebyreducing the cost of implementing the method.

The step of realigning the data signal within the wander buffer maycomprise replacing at least a portion of the data signal in the wanderbuffer with a copy of at least a portion of the frame alignment word.This takes advantage of the fact that the frame alignment word isgenerally known, and when the frame alignment word is detected it is notpayload data in the wander buffer; the data in the wander buffer may besafely replaced with a copy of the frame alignment word. Indeed, theportion of the data replaced will typically comprise received framealignment word only and not payload. This allows the amount of datastored within the wander buffer to be changed in order to realign thedata within the buffer. Preferably, the data in the wander buffer isrealigned to at least approximately half-fill the buffer.

As mentioned above, the position of the frame alignment word may bechecked in every frame received. Accordingly, the method may comprisedetermining the position of the frame alignment word in a first frame,determining the likely position of the frame alignment word in thereceived data signal in subsequent frames and looking for the framealignment word in the likely position in subsequent received frames. Asthe frame alignment word occurs in the same position in each frame, onceits position in one frame has been determined its position in subsequentframes and hence in the data signal is easily apparent.

Indeed, the method may comprise searching for a reduced portion of theframe alignment word in the subsequent frames. Such strategies reducethe processing load required. However, it is still preferred to searchfor the whole, or a substantial portion of, the frame alignment word inthe first frame, so as to avoid the detection of a mimic FAW; that is, aportion of the payload that coincidentally is identical to the true FAW.Once the frame alignment word has been detected it is less likely that apartial search in the correct place would be fooled by a mimic.

In a typical embodiment, the frame alignment word comprises a firstportion comprising the same data sequence repeated a plurality of times,followed by second portion repeated a plurality of times. In such acase, the reduced portion of the FAW may comprise searching for thetransition between the first and second portion; this is an easilyrecognisable change.

In the preferred embodiment, the data signal is a SDH or SONET datastream. This is particularly convenient when it is considered that SDHand SONET both have well defined frame alignment words.

According to a second aspect of the invention, there is provided acircuit for synchronising a serial data signal to a reference clocksignal, the data signal comprising frames of equal length eachcomprising a known frame alignment word (FAW) and a payload, the framealignment word being in a consistent position within each frame,comprising:

-   -   a data input and a data output;    -   a reference clock signal input;    -   a wander buffer comprising a FIFO memory;    -   a data aligner arranged to align, in use, a data signal input to        the data input to a reference clock signal input to the        reference clock signal input and to pass the aligned data signal        to the data output, the data aligned being coupled to the wander        buffer so as to store, in use the data signal during alignment        so as to compensate for any wander in the data signal; and    -   a frame alignment word detector arranged to detect the presence        of the frame alignment word, in use, in the data signal;    -   in which the circuit is arranged so as to realign the data        stored in the wander buffer once the frame alignment word        detector detects the presence of the frame alignment word in the        data signal.

The circuit may comprise a frame alignment word source, arranged suchthat when the circuit realigns the data stored in the wander buffer atleast a portion of the frame alignment word in the data signal isreplaced with a copy of the frame alignment word from the framealignment word source. This takes advantage of the fact that the framealignment word is generally known, and when the frame alignment word isdetected it is not payload data in the wander buffer; the data in thewander buffer may be safely replaced with a copy of the frame alignmentword. Indeed, the portion of the data replaced will typically comprisereceived frame alignment word only and not payload. This allows theamount of data stored within the wander buffer to be changed in order torealign the data within the buffer. Preferably, the data in the wanderbuffer is realigned to at least approximately half-fill the buffer.

The frame alignment word detector may be arranged so as to search forthe frame alignment word in every frame received. It may have twostates; a first state in which it searches for a first portion of theframe alignment word and determines the position of the frame alignmentwithin the data signal within a given frame, and a second state which itenters after determining the position of the frame alignment word in thedata signal in which it only searches for a second, reduced, portion ofthe frame alignment word but also predicts where the portion of theframe alignment word is likely to occur. As the frame alignment wordoccurs in the same position in each frame, once its position in oneframe has been determined its position in subsequent frames and hence inthe data signal is easily apparent.

Preferably, the circuit is arranged to carry out, in use, the method ofthe first aspect of the invention.

According to a third aspect of the invention, there is provided anetwork element comprising a plurality of circuits performing functionsof the network element; and internal serial interfaces between thecircuits; in which the circuits each comprise a circuit according to thesecond aspect of the invention coupled to an internal serial interfacethereof.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood and appreciated more fully fromthe following detailed description of an embodiment of the inventiontaken in conjunction with the drawings in which:

FIG. 1 is a diagram illustrating the frame structure of a serial dataframe;

FIG. 2 is a diagram illustrating a block diagram of a circuit accordingto an embodiment of the present invention; and

FIG. 3 is a diagram showing the changes made to the data signal as itpasses through the circuit of FIG. 2.

DESCRIPTION OF AN EMBODIMENT OF THE INVENTION

High speed serial interfaces rely on having a structured frame whichincludes a regularly repeating Frame Alignment Word (FAW). Each frame ofthe data stream can therefore be regarded as comprising the FAW and thepayload as shown in FIG. 1 of the accompanying drawings. The data streamcomprises many such frames in sequence. In the example of SDH or SONET,the FAW comprises a first portion comprising “F6” (depicted inhexadecimal) repeated 12 times followed by a second portion comprising“28” (depicted in hexadecimal) repeated 12 times.

This is made use of in the circuit shown in FIG. 2 of the accompanyingdrawings; the circuit forms an embodiment of the invention. A receiveddata signal is received at an input 1 of the circuit. It is passed to adynamic phase alignment (DPA) circuit 2, which chooses the optimum phaseto sample the received data signal. The data as input to the DPA isshown in FIG. 3 a. The output of this circuit is passed to FrameAlignment Word detector (FAW detector) 3, which searches for the FAW inthe data signal.

The FAW detector 3 has two states. The first state—the “out of frame”state—in which the FAW detector starts up, searches the entire datastream for the entire FAW. Accordingly, once the FAW has been detectedin this manner the FAW detector 3 can be reasonably certain that it hascorrectly located the FAW, and not a mimic, within a frame. Once the FAWhas been detected in the out of frame state, the FAW detector canproceed into the second, “in-frame” state as it knows where subsequentFAWs are likely to occur. In this state, the FAW detector only searchesthrough a window about the expected position and only searches for thetransition “F628” between the first and second portions of the FAW. TheFAW detector indicates to itself over data line 3 a when this state hasbeen entered.

The data signal is not changed by this search and passes through the FAWdetector to a FIFO wander buffer 4, depicted as an elastic store. Thisstores the data signal until it is the appropriate time to write it tothe output as will become apparent below. An input frame counter 5 keepstrack of the progress of the writing of the current frame into thewander buffer 4, and from this determines the correct write address forthe elastic store.

Early in the FAW, the FIFO within the DPA 2 is reset over line 5 b. Thiswill change the position of the FAW slightly within the recovered data,thus absorbing any wander that has occurred. The FAW detector 3 thenlocates the new position using the reduced FAW search. When it haslocated it, it indicates over line 3 a that the FAW has been found thewrite address is reset to a standard position halfway through the wanderbuffer. Accordingly, the write position into the wander buffer is resetto realign the data stored within the wander buffer 4.

This realignment can be seen in FIG. 3 b, where the FAW detector 3 hasinitiated a realignment and detected the presence of the FAW. Thiscauses some corruption of the data stored in the wander buffer 4; thisdoes not matter, as it is only ever the FAW that is corrupted.Furthermore, only a small portion—that indicated by ### in thedrawing—is corrupted.

The frame counter also notes if more than a frame's worth of data hasbeen written to the elastic store since the last realignment. If so,then the FAW detector must have missed a FAW, since they occur everyframe and the frame counter 5 initiates a reset of the entire circuitover line 5 c and the circuit restarts from its start up state.

Data from the wander buffer 4 is read out to an output 6 of the circuitthrough multiplexer 7. Read out of the data is controlled by an outputframe counter 8, which is connected to an input 9 for a reference clocksignal. This controls the read out of the data in the wander buffer 4 sothat it is read out in synchronisation with the reference clock. Thedata read out from the wander buffer 4, together with itssynchronisation to the system clock, is shown in FIG. 3 c of theaccompanying drawings. The output frame counter 8 controls the addressfrom which the data is read out of the elastic store.

However, there is still corrupted data in the signal read out. This iscorrected by use of a copy FAW store 10 also coupled to the multiplexer7. The FAW store 10 replaces the FAW received in each frame with alocally-stored copy, identical to the FAW transmitted in use without thecorruption introduced by the realignment process. This can be seen inFIG. 3 d of the accompanying drawings; it is to be noted that the“substitute frame alignment word” depicted therein is identical to the“frame alignment word” of FIGS. 3 a to 3 c. The output of the circuit istherefore a parallel, realigned version of the input signal, identicalin all other respects.

Accordingly, data signals received can be quickly and easilyresynchronised to a reference clock signal, with a reduced requirementfor the size of the wander buffer. The wander buffer need only be as bigas the amount of wander/jitter that can occur in a single frame.

1-18. (canceled)
 19. A method of synchronizing a serial data signal to a reference clock signal, the serial data signal comprising frames of equal length, each frame including a known frame alignment word (FAW) and a payload, the frame alignment word being located in a consistent position within each frame, the method comprising: storing a data signal in a First-In-First-Out (FIFO) wander buffer as the data signal is received to compensate for wander; outputting the data signal stored in the FIFO wander buffer synchronized to a reference clock signal; searching for at least a portion of the frame alignment word in the data signal as the data signal is received; and realigning the data signal within the wander buffer responsive to determining that the frame alignment word has been found.
 20. The method of claim 19 wherein realigning the data signal within the wander buffer comprises replacing at least a portion of the data signal in the wander buffer with a copy of at least a portion of the frame alignment word.
 21. The method of claim 20 wherein the copy of the portion of the frame alignment word is a locally stored copy of the frame alignment word.
 22. The method of claim 20 wherein the portion of the data signal replaced in the wander buffer comprises only the received frame alignment word.
 23. The method of claim 19 further comprising realigning the data signal in the wander buffer such that the data signal occupies approximately half the wander buffer.
 24. The method of claim 19 further comprising checking a position of the frame alignment word in every frame received.
 25. The method of claim 19 further comprising: determining a position of the frame alignment word in a first frame; determining a likely position of the frame alignment word in the received data signal in subsequent frames; and searching for the frame alignment word in the likely position in the subsequent frames.
 26. The method of claim 25 further comprising searching for a reduced portion of the frame alignment word in the subsequent frames.
 27. The method of claim 25 further comprising searching the first frame for one of the whole frame alignment word, and a substantial portion of the frame alignment word.
 28. The method of claim 26 wherein the frame alignment word comprises a first portion that includes a first data sequence repeated a plurality of times, followed by a second portion that includes a second data sequence repeated a plurality of times, and wherein searching for the reduced portion of the frame alignment word comprises searching for the transition between the first and second portion.
 29. The method of claim 19 wherein the data signal comprises at least one of an Synchronous Digital Hierarchy (SDH) data stream or a Synchronous optical networking (SONET) data stream.
 30. A circuit for synchronizing a serial data signal to a reference clock signal, the serial data signal comprising one or more frames of equal length, each comprising at a known frame alignment word (FAW) and a payload, the frame alignment word being located in a consistent position within each frame, the circuit comprising: a data input and a data output; a reference clock signal input; a wander buffer comprising a First-In-First-Out (FIFO) memory, and communicatively coupled to the data output; a data aligner configured to: align a data signal that is input to the data input to a reference clock signal that is input to the reference clock signal input; and pass the aligned data signal via the wander buffer to the data output, the wander buffer operative to store the data signal during alignment processing to compensate for wander in the data signal; and a frame alignment word detector configured to detect the presence of a frame alignment word in the data signal; wherein the circuit is configured to realign the data stored in the wander buffer responsive to the frame alignment word detector detecting the presence of the frame alignment word in the data signal.
 31. The circuit of claim 30 further comprising a frame alignment word source configured to replace at least a portion of the frame alignment word in the data signal with a copy of the frame alignment word from the frame alignment word source when the circuit realigns the data stored in the wander buffer.
 32. The circuit of claim 30 wherein the frame alignment word detector is further configured to search for the frame alignment word in every frame received.
 33. The circuit of claim 30 wherein the frame alignment word detector has two states, the states comprising: a first state in which the frame alignment word detector is configured to search for a first portion of the frame alignment word and determine a position of the frame alignment within the serial data signal within a given frame; and a second state in which the frame alignment word detector searches for a second, reduced portion of the frame alignment word and predicts where the portion of the frame alignment word is likely to occur, the frame alignment word detector entering the second state after determining the position of the frame alignment word in the first state.
 34. The circuit of claim 30 wherein the circuit is further configured to process at least one of a Synchronous Digital Hierarchy (SDH) and a Synchronous optical networking (SONET) data stream as the data signal.
 35. The circuit of claim 30 wherein the circuit is further configured to: store the data signal in a First-In-First-Out (FIFO) wander buffer as the data signal is received to compensate for wander; output the data signal stored in the FIFO wander buffer synchronized to the reference clock signal; search for at least a portion of the frame alignment word in the data signal as the data signal is received; and realign the data signal within the wander buffer responsive to determining that the frame alignment word has been found.
 36. A network element comprising: a plurality of circuits performing functions of the network element; internal serial interfaces between the plurality of circuits; and each of the plurality of circuits comprising: a data input and a data output; a reference clock signal input; a wander buffer comprising a First-In-First-Out (FIFO) memory, and communicatively coupled to the data output; a data aligner configured to: align a data signal that is input to the data input, to a reference clock signal that is input to the reference clock signal input; and pass the aligned data signal via the wander buffer to the data output, the wander buffer operative to store the data signal during alignment processing to compensate for wander in the data signal; and a frame alignment word detector configured to detect the presence of a frame alignment word in the data signal; wherein the circuit is configured to realign the data stored in the wander buffer responsive to the frame alignment word detector detecting the presence of the frame alignment word in the data signal. 